1. Field of the Invention
The present invention relates to a method for reducing stress of a sidewall oxide layer of a shallow trench isolation, and more particularly to a method for reducing stress of a sidewall oxide layer of a shallow trench isolation by annealing and reoxidation.
2. Description of the Related Art
As the density of integrated circuits increases, the dimension of an isolation region between active regions in semiconductor devices decreases. With this trend, the conventional local oxidation of silicon (LOCOS) method for isolating active regions, which forms a field oxide layer by using a thermal oxidation technique, confronts the limit in the effective isolation length, thereby degrading characteristics of the isolation region. Furthermore, the conventional LOCOS method possesses some inherent drawbacks resulting from the processes, i.e., lateral oxidation of the silicon underneath the silicon nitride mask, making the edge of the field oxide resemble the shape of a bird""s beak.
According to the disadvantages for LOCOS isolation structures mentioned above, an isolation technique using trenches has been developed. Generally, the trench isolation includes the steps of etching a silicon substrate to form a trench, depositing a oxide layer by using a chemical vapor deposition (CVD) process to fill up the trench, providing the oxide layer a planarized surface by using a chemical mechanical polish (CMP) process, and removing the oxide layer upon the active regions.
According to the technique, the semiconductor substrate is etched at a predetermined depth, thereby providing excellent characteristics of the device isolation. Furthermore, the field oxide layer is formed by using a CVD technique, so that the device isolation region that is defined by a photolithography process can be maintained throughout. The device isolation technique set forth is also known as shallow trench isolation (STI) processes.
However, conventional shallow trench isolation processes still have several drawbacks. FIG. 1 shows a cross-sectional diagram of a shallow trench isolation amid a STI conventional process. A silicon substrate 100, a silicon dioxide layers 102, a silicon nitride layer 104 are shown in FIG. 1. An oxide layer 106 is formed over the trench by conventional oxidation processes such as dry or wet thermal oxidation. The oxide layer 106 is used to eliminate etching induced damage and to reduce stress resulting from the following filling of silicon dioxide by conventional chemical vapor deposition. However, the oxide layer 106 itself is formed with large stress. This is because the conventional oxidation process, specially a wet oxidation process, always causes large stress within the oxide layer. The large stress usually presents defects in neighboring active regions. The defects will result in leakage current and degrade the reliability of neighboring devices.
In view of the drawbacks mentioned with the prior art process, there is a continued need to develop improved processes that overcome the disadvantages associated with prior art processes. The requirements of this invention are that it solves the problems mentioned above.
It is therefore an object of the invention to provide a method for reducing the stress of a sidewall oxide layer of a STI.
It is another object of this invention to provide a STI process which can assure the electrical property of the active regions.
It is a further object of this invention to provide a reliable STI process which can assure the isolation quality between the active regions.
To achieve these objects, and in accordance with the purpose of the invention, the invention uses a method comprising: providing a substrate having a first dielectric layer thereon and a second dielectric layer over said first dielectric layer; forming a trench into said substrate; forming a sidewall oxide layer on the sidewall and bottom of said trench; and performing an in situ steam generated process comprising introducing hydroxyl to anneal and reoxidize said sidewall oxide layer.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.